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atmel-8897d-dts-at30ts74-datasheet_102014 features ? single 1.7v to 5.5v supply ? measures temperature from -55 ? c to +125 ? c ? highly accurate temperature measurements requiring no external components ? 1.0 ? c accuracy (typical) over the -20 ? c to +100 ? c range ? 1.0 ? c accuracy (typical) over the -10 ? c to +100 ? c range (wlcsp only) ? 2.0 ? c accuracy (typical) over the -40 ? c to +125 ? c range ? user-configurable resolution ? 9 to 12 bits (0.5 ? c to 0.0625 ? c) ? user-configurable high and low temperature limits ? alert output pin for indicating temperature alarms ? 2-wire i 2 c and smbus ? compatible serial interface ? supports smbus timeout ? supports smbus alert and alert response address (ara) ? selectable addressing allows up to eight devices on the same bus ? i 2 c high-speed (hs) mode compatible ? 3.4mhz maximum clock frequency ? built-in noise suppression filtering for clock and data input signals ? low-power dissipation ? 85 a active current (typical) during temperature measurements ? shutdown mode to minimize power consumption ? 1 a shutdown current (typical) ? one-shot mode for single temperature measurement while in shutdown mode ? pin and software compatible to industry-standard lm75-type devices ? industry standard green (pb/halide-free/rohs compliant) package options ? 8-lead soic (150mil) ? 8-lead msop (3.0 x 3.0mm) ? 8-pad ultra thin dfn (udfn ? 2.0 x 3.0 x 0.6mm) ? 4-ball wlcsp at30ts74 9- to 12-bit selectable, 1.0c accurate digital temperature sensor preliminary datasheet
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 2 description the atmel ? at30ts74 is a complete, precise temperature monitoring device designed for use in a variety of applications which require the measuring of local temperatures as an integral part of the system's function and/or reliability. the at30ts74 device combines a high-precision digital temperature sensor, programmable high and low temperature alarms, and a 2-wire i 2 c and smbus (system management bus) compatible serial interface into a single compact package. the temperature sensor can measure temperatures over the full -55 ? c to +125 ? c temperature range and has a maximum accuracy of 2.0 ? c from -20 ? c to +100 ? c. the result of the digitized temperature measurements are stored in one of the at30ts74 internal registers, which is readable at any time through the device's serial interface. the at30ts74 utilizes flexible, user-programmable internal registers to configure the temperature sensor's performance and response to high and low temperature conditions. a dedicated alarm output activates if the temperature measurement exceeds the user-defined temperature and fault count limits. to reduce current consumption and save power, the at30ts74 features a shutdown mode which turns off all internal circuitry except for the internal power-on reset (por) and serial interface circuits. the at30ts74 is factory-calibrated and requires no external components to measure temperature. with its flexibility and high-degree of accuracy, the at30ts74 is ideal for extended temperature measurements in a wide variety of communication, computer, consumer, environmental, industrial, and instrumentation applications.
3 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 table of contents 1. pin descriptions and pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3. device communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.2 stop condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.3 acknowledge (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3.4 no-acknowledge (nack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.1 wlcsp (wafer level chip scale package) device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 high-speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 temperature measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 temperature alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4.1 fault tolerance limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4.2 comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.4.3 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.5 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.5.1 one-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5. registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 temperature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.3.1 os bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.2 r1:r0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.3 ft1:ft0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3.4 pol bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.5 cmp/int bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.3.6 sd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4 t low and t high limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. smbus features and i 2 c general call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.1 smbus alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.2 smbus timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3 general call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.2 dc and ac operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.4 temperature sensor accuracy and conversion characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.6 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.7 pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.8 input test waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.9 output test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 4 8. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.1 atmel ordering code detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.2 green package options (pb/halide-free/rohs compliant) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9. part marking detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10. packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.1 8s1 ? 8-lead jedec soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.2 8xm ? 8-lead msop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.3 8ma2 ? 8-pad udfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.4 4u-3 ? 4-ball wlcsp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11. errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.1 no errata. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 12. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
5 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 1. pin descriptions and pinouts table 1. pin description symbol name and function asserted state type scl serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command and input data present on the sda pin is always latched in on the rising edge of scl, while output data on the sda pin is always clocked out on the falling edge of scl. the scl pin must either be forced high when the serial bus is idle or pulled-high using an external pull-up resistor. ? input sda serial data: the sda pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. the sda pin must be pulled-high using an external pull-up resistor and may be wire-anded with any number of other open-drain or open-collector pins from other devices on the same bus. ? input/output alert alert: the alert pin is an open-drain output pin used to indicate when the temperature goes beyond the user-programmed temperature limits. the alert pin can be operated in one of two different modes (interrupt or comparator mode) as defined by the cmp/int bit in the configuration register. the alert pin defaults to an active-low output upon device power-up or reset but can be reconfigured as an active-high output by setting the pol bit in the configuration register. this pin can be wire-anded together with alert pins from other devices on the same bus. when wire-anding pins together, the alert pin should be configured as an active-low output so that when a single alert pin on the common alert bus goes active, the entire common alert bus will go low and the host controller will be properly notified since other alert pins that may be in the inactive-high state will not mask the true alert signal. in an smbus environment, the smbus host can respond by sending an smbus ara (alert response address) command to determine which device on the smbus generated the alert signal. the alert pin must be pulled-high using an external pull-up resistor even when it is not used. care must also be taken to prevent this pin from being shorted directly to ground without a resistor at any time whether during testing or normal operation. ? output a 2-0 address inputs: the a 2-0 pins are used to select the device address and correspond to the three least-significant bits (lsbs) of the i 2 c/smbus 7-bit slave address. these pins can be directly connected in any combination to v cc or gnd, and by utilizing the a 2-0 pins, up to eight devices may be addressed on a single bus. the a 2-0 pins are internally pulled to gnd and may be left floating; however, it is highly recommended the a 2-0 pins always be directly connected to v cc or gnd to ensure a known address state. for the 4-ball wlcsp offering, see section 4.1 for additional information. ? input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ? power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ? power
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 6 figure 1. pin configurations 2. block diagram figure 2-1. block diagram 8-soic (top view) 8-msop (top view) 8-udfn (top view) sda scl a lert gnd v cc a 0 a 1 a 2 sda scl alert gnd sda scl alert gnd v cc a 0 a 1 a 2 v cc a 0 a 1 a 2 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 note: package drawings are not to scale 4-ball wlcsp (top view) gnd sda scl v cc . i 2 c/smbus interface control and logic digital comparator pointer register configuration register t high limit register t low limit register temperature register a/d converter temperature sensor scl sda a 2-0 alert 3
7 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 3. device communication the at30ts74 operates as a slave device and utilizes a simple 2-wire i 2 c and smbus compatible digital serial interface to communicate with a host controller, commonly referred to as the bus master. the master initiates and controls all read and write operations to the slave devices on the serial bus, and both the master and the slave devices can transmit and receive data on the bus. the serial interface is comprised of just two signal lines: ? serial clock (scl): the scl pin is used to receive the clock signal from the master. ? serial data (sda): the bidirectional sda pin is used to receive command and data information from the master as well as to send data back to the master. data is always latched into the at30ts74 on the rising edge of scl and always output from the device on the falling edge of scl. both the scl and sda pin incorporate integrated spike suppression filters and schmitt triggers to minimize the effects of input spikes and bus noise. all command and data information is transferred with the most-significant bit (msb) first. during bus communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been transferred, the receiving device must respond with either an acknowledge (ack) or a no-acknowledge (nack) response bit during a ninth clock cycle (ack/nack clock cycle) generated by the master. therefore, nine clock cycles are required for every one byte of data transferred. there are no unused clock cycles during any read or write operation, so there must not be any interruptions or breaks in the data stream during each data byte transfer and ack or nack clock cycle. during data transfers, data on the sda pin must only change while scl is low, and the data must remain stable while scl is high. if data on the sda pin changes while scl is high, then either a start or a stop condition will occur. start and stop conditions are used to initiate and end all serial bus communication between the master and the slave devices. the number of data bytes transferred between a start and a stop condition is not limited and is determined by the master. in order for the serial bus to be idle, both the scl and sda pins must be in the logic-high state at the same time. 3.1 start condition a start condition occurs when there is a high-to-low transition on the sda pin while the scl pin is stable in the logic-high state. the master uses a start condition to initiate any data transfer sequence, and the start condition must precede any command. the at30ts74 will continuously monitor the sda and scl pins for a start condition, and the device will not respond unless one is given. 3.2 stop condition a stop condition occurs when there is a low-to-high transition on the sda pin while the scl pin is stable in the logic-high state. the master uses the stop condition to end a data transfer sequence to the at30ts74 which will subsequently return to the idle state. the master can also utilize a repeated start condition instead of a stop condition to end the current data transfer if the master will perform another operation. 3.3 acknowledge (ack) after every byte of data received, the at30ts74 must acknowledge to the master it has successfully received the data byte by responding with an ack. this is accomplished by the master first releasing the sda line and providing the ack/nack clock cycle (a ninth clock cycle for every byte). during the ack/nack clock cycle, the at30ts74 must output a logic 0 (ack) for the entire clock cycle such that the sda line must be stable in the logic-low state during the entire high period of the clock cycle.
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 8 3.4 no-acknowledge (nack) when the at30ts74 is transmitting data to the master, the master can indicate it is done receiving data and wants to end the operation by sending a nack response to the at30ts74 instead of an ack response. this is accomplished by the master outputting a logic 1 during the ack/nack clock cycle. at which point, the at30ts74 will release the sda line so the master can then generate a stop condition. in addition, the at30ts74 can use a nack to respond to the master instead of an ack for certain invalid operation cases such as an attempt to write to a read-only register (e.g. an attempt to write to the temperature register). figure 3-1. start, stop, and ack sck sda start condition data change allowed data change allowed data change allowed data change allowed ack stop condition data must be stable data must be stable data must be stable 1 28 9
9 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 4. device operation commands used to configure and control the operation of the at30ts74 are sent to the device from the master via the serial interface. likewise, the master can read the temperature data from the at30ts74 via the serial interface. however, since multiple slave devices can reside on the serial bus, each slave device must have its own unique 7-bit address so that the master can access each device independently. for the at30ts74, the first four msbs of its 7-bit address are the device type identifier and are fixed at 1001. the remaining three lsbs correspond to the states of the hard-wired a 2-0 address pins. for the wlcsp product offering, see section 4.1 for additional information on how the device address bits are handled. example: if the a 2-0 pins are connected to gnd, then the 7-bit device address would be 1001000. in order for the master to select and access the at30ts74, the master must first initiate a start condition. following the start condition, the master must output the device address byte. the device address byte consists of the 7-bit device address plus a read/write (r/ w) control bit, which indicates whether the master will be performing a read or a write to the at30ts74. if the r/ w control bit is a logic 1, then the master will be reading data from the at30ts74. alternatively, if the r/ w control bit is a logic 0, then the master will be writing data to the at30ts74. table 4-1. at30ts74 address byte if the 7-bit address sent by the master matches that of the at30ts74, then the device will respond with an ack after it has received the full address byte. if there is an address mismatch, then the at30ts74 will respond with a nack and return to the idle state. 4.1 wlcsp (wafer level chip scale package) device addressing the at30ts74 is offered in a space saving wlcsp to minimize pcb (printed circuit board) area requirements. because of the wlcsp dimensions and to maintain a standard ball size and pitch, only four balls can be placed on the wlcsp; therefore, there are no hard-wired a 2-0 device address pins (pins 5, 6, and 7) available like in other standard eight pin packages where the user can select the desired hard-wired device address combination. however, the at30ts74 wlcsp product is still available with all eight device address combinations via ordering a unique part number where each part number variant is internally configured by atmel with a different hard-wired a 2-0 address as shown in table 4-2 . example: if the desired hard-wired a 2-0 device address is 001, then the correct part number to order is the at30ts74-ufm11-t and this device will only ack when the master initiates a start condition followed by a device address byte with matching device address bits ( a2=0, a1=0, a0 =1) plus a read/write (r/ w) control bit. otherwise, the at30ts74 wlcsp will respond with a nack and return to the idle state. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device type identifier device address read/write 1 0 0 1 a2 a1 a0 r/ w
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 10 table 4-2. at30ts74 wlcsp device addresses note: please contact atmel for availability of slave address options 011,100,101,110, and 111. 4.2 high-speed mode the at30ts74 supports the i 2 c high-speed (hs) mode allowing it to operate at clock frequencies up to 3.4mhz. in order to put the at30ts74 into the hs mode, the master must first initiate a start condition followed by the hs mode master code of 00001xxx. since the hs mode master code is meant to be recognized by all slave devices which support the hs mode, the at30ts74 will not ack the hs mode master code. instead, the master will output a nack during the ack/nack clock cycle. once the at30ts74 receives the hs mode master code, it will switch its input filters on sda and scl to the hs mode to allow transfers up to 3.4mhz. the device will then return to the idle state and wait for a repeated start condition before the next operation can occur. to begin the next operation, the master must issue a repeated start condition followed by the device address byte. the at30ts74 will continue to operate in the hs mode until the master sends a stop condition; therefore, the master should use repeated start conditions to begin new operations rather than a stop-start sequence. once the at30ts74 receives a stop condition, the device will switch its input and output filters back to the standard i 2 c mode. figure 4-1. high-speed mode part number i 2 c address device type identifier a 2 a 1 a 0 r/ w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 at30ts74-ufm10-t 1001 000x 1 0 0 1 0 0 0 x at30ts74-ufm11-t 1001 001x 1 0 0 1 0 0 1 x at30ts74-ufm12-t 1001 010x 1 0 0 1 0 1 0 x at30ts74-ufm13-t 1001 011x 1 0 0 1 0 1 1 x at30ts74-ufm14-t 1001 100x 1 0 0 1 1 0 0 x at30ts74-ufm15-t 1001 101x 1 0 0 1 1 0 1 x at30ts74-ufm16-t 1001 110x 1 0 0 1 1 1 0 x at30ts74-ufm17-t 1001 111x 1 0 0 1 1 1 1 x sck sda master code start by master msb nack from master repeated start by master 1 2 3 4 5 6 7 8 9 0 0 0 0 1 x x x 1
11 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 4.3 temperature measurements the at30ts74 utilizes a band-gap type temperature sensor with an internal sigma-delta analog-to-digital converter (adc) to measure and convert the temperature reading into a digital value with a selectable resolution as high as 0.0625 ? c. the measured temperature is calibrated in degrees celsius; therefore, a lookup table or conversion routine is necessary for applications that wish to deal in degrees fahrenheit. the result of the digitized temperature measurements are stored in the internal temperature register of the at30ts74, which is readable at any time through the device's serial interface. when in the normal operating mode, the device performs continuous temperature measurements and updates the contents of the temperature register (see section 5.2, ?temperature register? ) after each analog-to-digital conversion. the resolution of the temperature measurement data can be configured to 9, 10, 11, or 12 bits which corresponds to temperature increments of 0.5 ? c, 0.25 ? c, 0.125 ? c, and 0.0625 ? c, respectively. selecting the temperature resolution is done using the r1 and r0 bits in the configuration register (see section 5.3, ?configuration register? ). the adc conversion time does increase with each bit of higher resolution, so careful consideration should be given to the resolution versus conversion time relationship. the default resolution after device power-up or reset is nine bits, which retains backwards compatibility to industry-standard lm75-type devices. with 12 bits of resolution, the at30ts74 can theoretically measure a temperature range of 255 ? c (-128 ? c to +127 ? c); however, the device is only designed to measure temperatures over a range of -55 ? c to +125 ? c. 4.4 temperature alarm after the measured temperature value has been stored into the temperature register, the data will be compared with both the high and low temperature limits defined by the values stored in the t high limit register and t low limit register. if the comparison results in a valid fault condition (see section 4.4.1, ?fault tolerance limits? ), then the device will activate the alert output pin. the polarity and function of the alert pin can be configured by using specific bits in the configuration register. the alert pin defaults to the active low state after device power-up or reset but can be reconfigured to active high by setting the pol bit in the configuration register to a logic 1. the function of the alert pin changes based on the alarm thermostat mode, which can be configured to either comparator mode (see section 4.4.2, ?comparator mode? ) or interrupt mode (see section 4.4.3, ?interrupt mode? ) by using the cmp/int bit in the configuration register. the comparator mode is the default operating mode after the device powers up or resets. the value of the high temperature limit stored in the t high limit register must be greater than the value of the low temperature limit stored in the t low limit register in order for the alert function to work properly; otherwise, the alert pin will output erroneous results and will falsely signal temperature alarms. 4.4.1 fault tolerance limits a temperature fault occurs if the measured temperature meets or exceeds either the high temperature limit set by the t high limit register or the low temperature limit set by the t low limit register. to prevent false alarms due to environmental or temperature noise, the device incorporates a fault tolerance queue that requires consecutive temperature faults to occur before resulting in a valid fault condition. the fault tolerance queue value is controlled by the ft1 and ft0 bits in the configuration register and can be set to a single fault count of 1 or a count of 2, 4, or 6 consecutive faults. an internal counter that automatically increments after a temperature fault is used to determine if the fault tolerance queue setting has been met. after incrementing the fault counter, the device will compare the count to the fault tolerance queue setting to see if a valid fault condition should be triggered. once a valid fault condition occurs, the device will activate the alert output pin. if the most recent measured temperature does not meet or exceed the high or low temperature limit, then the internal fault counter will be reset back to zero.
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 12 figure 4-2 shows a sample temperature profile and how each temperature fault would impact the internal fault counter. figure 4-2. fault count example 4.4.2 comparator mode when the device operates in the comparator mode, then the alert pin goes active if the measured temperature meets or exceeds the high temperature limit set by the t high limit register and a valid fault condition exists (the consecutive number of temperature faults has been reached). the alert pin will return to the inactive state after the measured temperature drops below the t low limit register value the appropriate number of times to create a subsequent valid fault condition. the alert pin only changes state based on the high and low temperature limits and fault conditions; reading from or writing to any register or putting the device into shutdown mode will not affect the state of the alert pin. the high temperature limit set by the t high limit register must be greater than the low temperature limit set by the t low limit register in order for the alert pin to activate correctly. if switching from interrupt mode to comparator mode while the alert pin is already active, then the alert pin will remain active until the measured temperature is below the t low limit register value the appropriate number of times to create a valid fault condition. the alert pin will return to the inactive state if the device receives the general call reset command. in addition, the state of the configuration register will return to the power-on default state, and the device will remain in the comparator mode. figure 4-3 illustrates both the active high and active low alert pin response for a sample temperature profile with the device configured for the comparator mode and a fault tolerance queue setting of two. temperature measurements/conversions t high limit temperature t low limit
13 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 figure 4-3. comparator mode (fault tolerance queue = 2) 4.4.3 interrupt mode similar to the comparator mode, when the device operates in the interrupt mode, the alert pin will go active if the measured temperature meets or exceeds the high temperature limit set by the t high limit register and a valid fault condition exists (the consecutive number of temperature faults has been reached). unlike the comparator mode, however, the alert pin will remain active until one of three normal operation events takes place: any one of the device's registers is read, the device responds to an smbus alert response address (ara), or the device is put into shutdown mode. once the alert pin returns to the inactive state, it will not go active again until the measured temperature drops below the low temperature limit set by the t low limit register for the appropriate number of consecutive faults. again, the alert pin will remain active until one of the device's registers is read, the device responds to an smbus ara, or the device is placed into the shutdown mode. after the alert pin becomes inactive again, the cycle will repeat itself with the alert pin going active after the measured temperature meets or exceeds the t high limit register value for the proper number of consecutive faults. this process is cyclical between t high and t low temperature alarms (e.g. t high event, alert clear, t low event, alert clear, t high event, alert clear, t low event, etc.). in order for the alert pin to normally become active for the first time in the interrupt mode, the first event must be a t high temperature alarm event. therefore, even if the measured temperature initially starts off between the t high and t low limits and then drops below the t low temperature limit and has met valid fault conditions, the alert pin will still not go active. the high temperature limit set by the t high limit register must be greater than the low temperature limit set by the t low limit register in order for the alert pin to activate correctly. if switching from comparator mode to interrupt mode while the alert pin is already active, then the alert pin will remain active until it is cleared by one of the events already detailed: any one of the device's registers is read, the device responds to an smbus ara, or the device is put into shutdown mode. the alert pin will also return to the inactive state if the device receives the general call reset command. when reset, the state of the configuration register will return to the power-on default state which will put the device back into the comparator mode. temperature measurements/conversions t high limit temperature t low limit alert (active high, pol = 1) alert (active low, pol = 0)
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 14 figures 4-4 and figure 4-5 show both the active high and active low alert pin response for a sample temperature profile with the device configured for the interrupt mode and a fault tolerance queue setting of two. figure 4-5 illustrates how the alert pin output would look if there was a longer delay between the alert trigger and the reading of a register. figure 4-4. interrupt mode (fault tolerance queue = 2) figure 4-5. interrupt mode (fault tolerance queue = 2) delay before reading register temperature measurements/conversions t high limit temperature t low limit alert (active high, pol = 1) alert (active low, pol = 0) read register read register read register temperature measurements/conversions t high limit temperature t low limit alert (active high, pol = 1) alert (active low, pol = 0) read register read register
15 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 4.5 shutdown mode to reduce current consumption and save power, the device features a shutdown mode that disables all internal device circuitry except for the serial interface and por circuits. while in the shutdown mode, the internal temperature sensor is not active, so no temperature measurements will be made. entering and exiting the shutdown mode is controlled by the sd bit in the configuration register. entering the shutdown mode can affect the alert pin depending on the alarm thermostat mode. if the device is configured to operate in the interrupt mode, then the alert pin will go inactive when the device enters the shutdown mode. however, the alert pin will not change states if the device is operating in the comparator mode. the fault count information will not change when the device enters or exits the shutdown mode. therefore, the number of previous temperature faults recorded by the internal fault counter will be retained unless the device is power-cycled or reset. when exiting the shutdown mode, the alert pin will go active if operating in interrupt mode, a valid fault condition exists, and the t high and t low event cycles are maintained (i.e. t high event before entering shutdown mode followed by a t low event when exiting shutdown mode). 4.5.1 one-shot mode the at30ts74 features a one-shot temperature mode that allows the device to perform a single temperature measurement while in the shutdown mode. by keeping the device in the shutdown mode and utilizing the one- shot mode, the at30ts74 can remain in a lower power state and only go active to take temperature measurements on an as-needed basis. the internal fault counter will be updated when taking a temperature measurement using the one-shot mode; therefore, a valid fault condition can be generated by the one-shot temperature measurements. if operating in comparator mode, then the fault condition will cause the alert pin to go either active or inactive depending on if the fault condition is a result of a t high or t low event. if operating in interrupt mode, the fault condition will cause the alert pin to pulse active for a short duration of time to indicate a t high or t low event has occurred. the alert pin will then return to the inactive state. the one-shot mode is controlled using the os bit in the configuration register (see section 5.3.1, ?os bit? ).
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 16 5. registers the at30ts74 contains five registers (a pointer register and four data registers) that are used to control the operational mode and performance of the temperature sensor, store the user-defined high and low temperature limits, and store the digitized temperature measurements. all accesses to the device are performed using these five registers. in order to read from and write to one of the device's four data registers, the user must first select a desired data register by utilizing the pointer register. table 5-1. registers the configuration register, despite being 16-bits wide, is compatible to industry standard lm75-type temperature sensors that use an 8-bit wide register in that only the first 8-bits of the configuration register need to be written to or read from. 5.1 pointer register the 8-bit write-only pointer register is used to address and select which one of the device's four data registers (temperature register, configuration register, t low limit register, or t high limit register) will be read from or written to. for read operations from the at30ts74, once the pointer register is set to point to a particular data register, it remains pointed to that same data register until the pointer register value is changed. example: if the user sets the pointer register to point to the temperature register, then all subsequent reads from the device will output data from the temperature register until the pointer register value is changed. for write operations to the at30ts74, the pointer register value must be refreshed each time a write to the device is to be performed, even if the same data register is going to be written to a second time in a row. example: if the pointer register is set to point to the configuration register, once the subsequent write operation to the configuration register has completed, the user cannot write again into the configuration register without first setting the pointer register value again. as long as a write operation is to be performed, the device will assume that the pointer register value is the first data byte received after the address byte. since only four data registers are available for access, only the two lsbs (p1 and p0) of the pointer register are used; the remaining six bits (p7-p2) of the pointer register should always be set to zero to allow for future migration paths to other temperature sensor devices that have more than four data registers. table 5-2 shows the bit assignments of the pointer register and the associated pointer addresses of the data registers available. attempts to write any values other than those listed in table 5-2 into the pointer register will be ignored by the device, and the contents of the pointer register will not be changed. however, the device will respond back to the master with an ack to indicate that the device successfully received a data byte even though no operation will be performed. register address read/write size power-on default pointer register n/a w 8-bit 00h temperature register 00h r 16-bit 0000h configuration register 01h r/w 16-bit 0000h t low limit register 02h r/w 16-bit 4b00h (75 ? c) t high limit register 03h r/w 16-bit 5000h (80 ? c)
17 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 table 5-2. pointer register and address assignments to set the value of the pointer register, the master must first initiate a start condition followed by the at30ts74 device address byte (1001aaa0 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the at30ts74 has received the proper address byte, the device will send an ack to the master. the master must then send the appropriate data byte to the at30ts74 to set the value of the pointer register. after device power-up or reset, the pointer register defaults to 00h which is the temperature register location; therefore, the temperature register can be read from immediately after device power-up or reset without having to set the pointer register. figure 5-1. write pointer register 5.2 temperature register the temperature register is a 16-bit read-only register that stores the digitized value of the most recent temperature measurement. the temperature data value is represented in the twos complement format, and, depending on the resolution selected, up to 12 bits of data will be available for output with the remaining lsbs being fixed in the logic 0 state. the temperature register can be read at any time, and since temperature measurements are performed in the background, reading the temperature register does not affect any other operation that may be in progress. the msb (bit 15) of the temperature register contains the sign bit of the measured temperature value with a zero indicating a positive number and a one indicating a negative number. the remaining msbs of the temperature register contain the temperature value in the twos complement format. table 5-3 details the temperature register format for the different selectable resolutions, and table 5-4 shows some examples for 12-bit resolution temperature register data values and the associated temperature readings. pointer register value associated address register selected p7 p6 p5 p4 p3 p2 p1 p0 0 0 0 0 0 0 0 0 00h temperature register 0 0 0 0 0 0 0 1 01h configuration register 0 0 0 0 0 0 1 0 02h t low limit register 0 0 0 0 0 0 1 1 03h t high limit register sck sda address byte pointer register byte start by master ack from slave msb msb ack from slave stop by master 1 0 0 1 a a a 0 0 p7 p6 p5 p4 p3 p2 p1 p0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 18 table 5-3. temperature register format note: td = temperature data table 5-4. 12-bit resolution temperature data/values examples after each temperature measurement and digital conversion is complete, the new temperature data is loaded into the temperature register if the register is not currently being read. if a read is in progress, then the previous temperature data will be output. resolution upper byte lower byte bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12 bits sign td td td td td td td td td td td 0 0 0 0 11 bits sign td td td td td td td td td td 0 0 0 0 0 10 bits sign td td td td td td td td td 0 0 0 0 0 0 9 bits sign td td td td td td td td 0 0 0 0 0 0 0 temperature register data temperature binary value hex value +125c 0111 1101 0000 0000 7d00h +100c 0110 0100 0000 0000 6400h +75c 0100 1011 0000 0000 4b00h +50.5c 0011 0010 1000 0000 3200h +25.25c 0001 1001 0100 0000 1940h +10.125c 0000 1010 0010 0000 0a20h +0.0625c 0000 0000 0001 0000 0010h 0c 0000 0000 0000 0000 0000h -0.0625c 1111 1111 1111 0000 fff0h -10.125c 1111 0101 1110 0000 f5e0h -25.25c 1110 0111 1100 0000 e7c0h -50.5c 1100 1110 1000 0000 ce80h -55c 1100 1001 0000 0000 c900h
19 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 in order to read the most recent temperature measurement data, the pointer register must be set or have been previously set to 00h. if the pointer register has already been set to 00h, the temperature register can be read by having the master first initiate a start condition followed by the at30ts74 device address byte (1001aaa1 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the at30ts74 has received the proper address byte, the device will send an ack to the master. the master can then read the upper byte of the temperature register. after the upper byte of the temperature register has been clocked out of the at30ts74, the master must send an ack to indicate that it is ready for the lower byte of the temperature data. the at30ts74 will then clock out the lower byte of the temperature register, after which the master must send a nack to end the operation. when the at30ts74 receives the nack, it will release the sda line so that the master can send a stop or repeated start condition. if the master does not send a nack but instead sends an ack after the lower byte of the temperature register has been clocked out, then the device will repeat the sequence by outputting new temperature data starting with the upper byte of the temperature register. if 8-bit temperature resolution is satisfactory, then the lower byte of the temperature register does not need to be read. in this case, the master would send a nack instead of an ack after the upper byte of the temperature register has been clocked out of the at30ts74. when the at30ts74 receives the nack, the device will know that it should not send out the lower byte of the temperature register and will instead release the sda line so the master can send a stop or repeated start condition. the temperature register defaults to 0000h after device power-up or reset; therefore, the system should wait the maximum conversion time (t conv ) for the selected resolution before attempting to read valid temperature data. since the temperature register is a read-only register, any attempts to write to the register will be ignored, and the device will subsequently respond by sending a nack back to the master. figure 5-2. read temperature register ? 16 bits note: assumes the pointer register was previously set to point to the temperature register. figure 5-3. read temperature register ? 8 bits note: assumes the pointer register was previously set to point to the temperature register. sck sda address byte temperature register upper byte temperature register lower byte start by master ack from slave ack from master msb msb nack from master stop by master msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 1 sck sda address byte temperature register upper byte start by master ack from slave msb msb nack from master stop by master 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 1
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 20 5.3 configuration register the configuration register is used to control key operational modes and settings of the device such as the one-shot mode, the temperature conversion resolution, the fault tolerance queue, the alert pin polarity, the alarm thermostat mode, and the shutdown mode. the configuration register is a 16-bit wide read/write register; however, only the first 8-bits of the register are actually used while the least-significant 8-bits are reserved for future use to provide an upward migration path to other temperature sensor devices that have enhanced features. since only the most-significant eight bits of the configuration register are used, the device is backwards compatible to industry standard lm75-type temperature sensors that use 8-bit wide registers. after device power-up or reset, the configuration register defaults to 0000h; therefore, the system should update the configuration register with the desired settings prior to attempting to read the temperature register unless the default configuration register settings are satisfactory for the application. table 5-5. configuration register to set the value of the configuration register, the master must first initiate a start condition followed by the at30ts74's device address byte (1001aaa0 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the at30ts74 has received the proper address byte, the device will send an ack to the master. the master must then send the appropriate pointer register byte of 01h to select the configuration register. after the pointer register byte of 01h has been sent, the at30ts74 will send another ack to the master. after receiving the ack from the at30ts74, the master must then send the appropriate data byte to the at30ts74 bit name type description 15 os one-shot mode r/w 0 normal operation (default) 1 perform one-shot measurement (valid in shutdown mode only) 14:13 r1:r0 conversion resolution r/w 00 9-bits (default) 01 10-bits 10 11-bits 11 12-bits 12:11 ft1:ft0 fault tolerance queue r/w 00 alarm after 1 fault (default) 01 alarm after 2 consecutive faults 10 alarm after 4 consecutive faults 11 alarm after 6 consecutive faults 10 pol alert pin polarity r/w 0 alert pin is active low (default) 1 alert pin is active high 9 cmp/int alarm thermostat mode r/w 0 comparator mode (default) 1 interrupt mode 8 sd shutdown mode r/w 0 temperature sensor performing active measurements (default) 1 temperature sensor disabled and device in shutdown mode 7:0 rfu reserved for future use r 0 reserved for future use
21 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 to set the value of the configuration register. only the first data byte sent to the at30ts74 will be recognized as valid data; any subsequent bytes received by the device will simply be ignored. if the master does not send a complete byte of configuration register data prior to issuing a stop or repeated start condition, then the at30ts74 will ignore the data and the contents of the configuration register will be unchanged. 5.3.1 os bit the os bit is used to enable the one-shot temperature measurement mode. when a logic 1 is written to the os bit while the at30ts74 is in the shutdown mode, the device will become active and perform a single temperature measurement and conversion. after the temperature register has been updated with the measured temperature data, the device will return to the low-power shutdown mode and clear the os bit. writing a one to the os bit when the device is not in the shutdown mode will have no affect. when reading the configuration register, the os bit will always be read as a logic 0. 5.3.2 r1:r0 bits the r1 and r0 bits are used to select the conversion resolution of the internal sigma-delta adc. four possible resolutions can be set to maximize for either higher resolution or faster conversion times. the r1 and r0 bits default to the logic 0 state after device power-up or reset to retain backwards compatibility to industry-standard lm75-type devices. table 5-6. conversion resolution 5.3.3 ft1:ft0 bits the ft1 and ft0 bits are used to set the fault tolerance queue value which defines how many consecutive faults must occur before the alert pin will be activated (see section 4.4.1, ?fault tolerance limits? ). the ft1 and ft0 bit settings provide four different fault values as detailed in table 5-7 . after the device powers up or resets, both the ft1 and ft0 bits will default to the logic 0 state. table 5-7. fault tolerance queue r1 r0 conversion resolution conversion time 0 0 9 bits 0.5c 25ms 0 1 10 bits 0.25c 50ms 1 0 11 bits 0.125c 100ms 1 1 12 bits 0.0625c 200ms nvft1 nvft0 consecutive faults required 0 0 1 0 1 2 1 0 4 1 1 6
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 22 5.3.4 pol bit the alert pin polarity is controlled by the pol bit. when the pol bit is in the logic 0 state, the alert pin will be an active low output (the default setting after device power-up or reset). to configure the alert pin as an active high output, the pol bit must be set to the logic 1 state. 5.3.5 cmp/int bit the cmp/int bit controls whether the device will operate in the comparator mode or the interrupt mode. setting the cmp/int bit to the logic 0 state will put the device into the comparator mode (default after device power-up or reset). alternatively, when the cmp/int bit is set to the logic 1 state, then the device will operate in the interrupt mode. the function of the alert pin changes based on the cmp/int bit setting. 5.3.6 sd bit the sd bit is used to enable or disable the device's shutdown mode. when the sd bit is in the logic 0 state (default after device power-up or reset), the device will be in the normal operational mode and perform continuous temperature measurements and conversions. when the sd bit is set to the logic 1 state, the device will finish the current temperature measurement and conversion and will store the result in the temperature register, after which the device will then enter the shutdown mode. resetting the sd bit back to a logic 0 will return the device to the normal operating mode. figure 5-4. write to configuration register figure 5-5. read from configuration register note: assumes the pointer register was previously set to point to the configuration register. sck sda address byte pointer register byte configuration register upper byte start by master ack from slave ack from slave msb msb ack from slave stop by maste r msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 0 0 0 0 0 0 0 0 0 1 0 d15 d14 d13 d12 d11 d10 d9 d8 0 sck sda start by master ack from slave nack from master address byte configuration register upper byte stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 1
23 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 5.4 t low and t high limit registers the 16-bit t low and t high limit registers store the user-programmable lower and upper temperature limits for the temperature alarm. like the temperature register, the temperature data values of the t low and t high limit registers are stored in the twos complement format with the msb (bit 15) of the registers containing the sign bit (zero indicates a positive number and a one indicates a negative number). as with the temperature register, the resolution selected by the r1 and r0 bits of the configuration register will determine how many bits of the t low and t high limit registers will be used. therefore, when writing to the t low and t high limit registers, up to 12 bits of data will be recognized by the device with the remaining lsbs being internally fixed to the logic 0 state. similarly, when reading from the registers, up to 12 bits of data will be output from the device with the remaining lsbs fixed in the logic 0 state. table 5-8. t low limit register and t high limit register format note: td = temperature data to set the value of either the t low or t high limit register, the master must first initiate a start condition followed by the at30ts74 device address byte (1001aaa0 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the at30ts74 has received the proper address byte, the device will send an ack to the master. the master must then send the appropriate pointer register byte of 02h to select the t low limit register or 03h to select the t high limit register. after the pointer register byte has been sent, the at30ts74 will send another ack to the master. after receiving the ack from the at30ts74, the master must then send two data bytes to the at30ts74 to set the value of the t low or t high limit register. any subsequent bytes sent to the at30ts74 will simply be ignored by the device. if the master does not send two complete bytes of data prior to issuing a stop or repeated start condition, then the at30ts74 will ignore the data and the contents of the register will not be changed. in order to read the t low or t high limit register, the pointer register must be set or have been previously set to 02h to select the t low limit register or 03h to select the t high limit register (if the previous operation was a write to one of the registers, then the pointer register will already be set for that particular limit register). if the pointer register has already been set appropriately, the t low or t high limit register can be read by having the master first initiate a start condition followed by the at30ts74 device address byte (1001aaa1 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the at30ts74 has received the proper address byte, the device will send an ack to the master. the master can then read the upper byte of the t low or t high limit register. after the upper byte of the register has been clocked out of the at30ts74, the master must send an ack to indicate that it is ready for the lower byte of data. the at30ts74 will then clock out the lower byte of the register, after which the master must send a nack to end the operation. when the at30ts74 receives the nack, it will release the sda line so that the master can send a stop or repeated start condition. if the master does not send a nack but instead sends an ack after the lower byte of the register has been clocked out, then the device will repeat the sequence by outputting the data again starting with the upper byte of the register. resolution upper byte lower byte bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12 bits sign td td td td td td td td td td td 0 0 0 0 11 bits sign td td td td td td td td td td 0 0 0 0 0 10 bits sign td td td td td td td td td 0 0 0 0 0 0 9 bits sign td td td td td td td td 0 0 0 0 0 0 0
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 24 the t low limit register defaults to 4b00h (+75c) and the t high limit register defaults to 5000h (+80c) after the device powers up or resets; therefore, both registers will need to be modified after power-up/reset if these default temperature limits are not satisfactory for the application. the value of the high temperature limit stored in the t high limit register must be greater than the value of the low temperature limit stored in the t low limit register in order for the alert function to work properly; otherwise, the alert pin will output erroneous results and will falsely signal temperature alarms. in addition, changing either value of the t high or t low limit register will cause the internal fault counter to reset back to zero. figure 5-6. write to t low or t high limit register figure 5-7. read from t low or t high limit register note: assumes the pointer register was previously set to point to the t low or t high limit register. sck sda start by master ack from slave ack from slave address byte t low or t high limit register upper byte t low or t high limit register lower byte pointer register byte msb msb ack from slave ack from slave stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 0 0 0 0 0 0 0 0 p1 p0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 0 sck sda start by master ack from slave nack from master stop by master ack from master address byte t low or t high limit register upper byte t low or t high limit register lower byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 1 msb msb msb
25 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 6. smbus features and i 2 c general call 6.1 smbus alert the at30ts74 utilizes the alert pin to support the smbus alert function when the alarm thermostat mode is set to the interrupt mode (the cmp/int bit of the configuration register is set to one) and the alert pin polarity is set to active low (the pol bit of the configuration register is set to zero). the at30ts74 is a slave-only device, and normally, slave devices on the smbus cannot signal to the master that they want to communicate. however, the at30ts74 uses the smbus alert function (the alert pin) to signal to the master that it wants to communicate. several smbus alert pins from different slave devices can be connected to a common smbus alert input on the master. when the smbus alert input on the master is pulled low by one of the slave devices, the master can perform a specialized read operation from the slave devices to determine which device sent the smbus alert signal. the specialized read operation is known as an smbus ara and requires that the master first initiate a start condition followed by the smbus ara code of 00011001. the slave device that generated the smbus alert signal will respond to the master with an ack. after sending the ack, the slave device will then output its own device address (1001aaa for the at30ts74 where ?aaa? corresponds to the hard-wired a 2-0 address pins) on the bus. since the device address is seven bits long, the remaining eighth bit (the lsb) is used as an indicator to notify the master which temperature limit caused the alarm (the lsb will be a logic 1 if the t high limit was met or exceeded, and the lsb will be a logic 0 if the t low limit was exceeded). the smbus ara can activate several slave devices at the same time; therefore, if more than one slave responds, standard smbus arbitration rules apply and the device with the lowest address wins the arbitration. the device winning the arbitration will clear its smbus alert output after it has responded to the smbus ara and provided its device address. all other devices with higher addresses do not generate an ack and continue to hold their smbus alert outputs low until cleared. the master will continue to issue smbus ara sequences until all slave devices which generated an smbus alert signal have responded and cleared their smbus alert outputs. figure 6-1. smbus alert note: the limit bit (the lsb) of the device address byte will be one or zero depending on if the t high or t low limit was exceeded. sck sda smbus ara code at30ts74 device address byte start by master ack from slave nack from master stop by master msb msb 0 0 0 1 1 0 0 1 0 1 0 0 1 a2 a1 a0 limit 1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 26 6.2 smbus timeout the at30ts74 supports the smbus timeout feature in which the at30ts74 will reset its serial interface and release the smbus (stop driving the bus and let sda float high) if the scl pin is held low for more than the minimum t timeout specification. the at30ts74 will be ready to accept a new start condition before t timeout maximum has elapsed. figure 6-2. smbus timeout 6.3 general call the at30ts74 will respond to an i 2 c general call address (0000000) from the master only if the eighth bit (the lsb) of the general call address byte is zero. if the general call address byte is 00000000, then the device will send an ack to the master and await a command byte from the master. if the master sends a command byte of 04h, then the at30ts74 will re-latch the status of its address pins in case the system has assigned a new address to the device. if the master sends a command byte of 06h (general call reset), then the at30ts74 will re-latch the status of its address pins and perform a reset sequence. the reset sequence will reset all registers to their power-up defaults, and the device will be busy for a maximum time of t por during the reset operation. device will release bus and be ready to accept a new start condition within this time t timeout (max) t timeout (min) scl
27 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 7. electrical specifications 7.1 absolute maximum ratings* 7.2 dc and ac operating range notes: 1. device operation is guaranteed from -40c to +125c. 2. device operation is not guaranteed at -55c but ensured by characterization. temperature under bias. . . . . . . . -40c to +125c storage temperature . . . . . . . . . . -65c to +150c supply voltage with respect to ground . . . . . . . . . . . -0.5v to +7.0v alert pin . . . . . . . . . . . . . . . . -0.5v to v cc + 0.3v all input voltages with respect to ground . . . . . . . -0.5v to v cc + 0.5v all other output voltages with respect to ground . . . . . . . -0.5v to v cc + 0.5v *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these ratings or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage extremes referenced in the ?absolute maximum ratings? are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time. pull-up voltages applied to the alert pin that exceed the ?absolute maximum ratings? may forward bias to the esd protection circuitry. doing so may result in improper device function and may corrupt temperature measurements. at30ts74 operating temperature (case) industrial high temperature -55 ? c to +125 ? c (1)(2) v cc power supply 1.7v to 5.5v
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 28 7.3 dc characteristics note: 1. typical values characterized at t a = +25c at v cc = 1.8v, 3.0v and 5.0v unless otherwise noted. symbol parameter v cc range condition min typ (1) max units i cc1 active current, bus inactive 1.7v v cc 2.0v active temperature conversions 60 85 a 2.7v v cc 3.6v 65 95 4.5v v cc 5.5v 85 125 i cc2 active current, bus active 1.7v v cc 2.0v active temperature conversions, f scl = 400khz 120 160 a 2.7v v cc 3.6v 150 225 4.5v v cc 5.5v 225 325 i cc3 active current, bus active 2.2v v cc 3.6v active temperature conversions, f scl = 3.4mhz 235 500 a 4.5v v cc 5.5v 610 800 i sd1 shutdown mode current, bus inactive 1.7v v cc 2.0v 0.4 2.5 a 2.7v v cc 3.6v 0.6 3.5 4.5v v cc 5.5v 1.2 5.5 i sd2 shutdown mode current, bus active 1.7v v cc 2.0v f scl = 400khz 110 160 a 2.7v v cc 3.6v 130 200 4.5v v cc 5.5v 180 280 i sd3 shutdown mode current, bus active 2.2v v cc 3.6v f scl = 3.4mhz 210 425 a 4.5v v cc 5.5v 550 750 i li input leakage current v in = cmos levels 1 a i lo output leakage current v out = cmos levels 1 a v il input low voltage 0.3 x v cc v v ih input high voltage 0.7 x v cc v v ol1 output low voltage i ol = 3ma 0.4 v v ol2 output low voltage, alert pin i ol = 4ma 0.4 v
29 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 7.4 temperature sensor accuracy and conversion characteristics notes: 1. typical values characterized at v cc = 3.3v, t a = +25c unless otherwise noted. 2. sensor accuracy characterized to this range but not tested or guaranteed. 7.5 ac characteristics notes: 1. these parameters are determined through product characterization and are not tested 100% in production. 2. minimum clock frequency must be at least 1khz to avoid activating the smbus timeout feature. symbol parameter condition min typ (1) max units t acc sensor accuracy t a = -20c to +100c 1.0 2.0 ? c t a = -10c to +100c, wlcsp 1.0 2.0 t a = -40c to +125c 2.0 3.0 t a = -55c to +125c (2) 3.0 t res conversion resolution selectable 9 to 12 bits 0.5 (9 bits) 0.0625 (12 bits) ? c t conv conversion time 9-bit resolution 25 37.5 ms 10-bit resolution 50 75 11-bit resolution 100 150 12-bit resolution 200 300 symbol parameter v cc = 1.7v to 3.6v v cc < 2.2v v cc = 2.2v to 3.6v units fast mode fast mode plus high-speed mode min max min max min max f scl serial clock frequency 1 (2) 400 1 (2) 1000 1 (2) 3400 khz t sclh clock high time 600 260 60 ns t scll clock low time 1300 500 160 ns t r clock/data input rise time (1) 300 120 100 ns t f clock/data input fall time (1) 300 120 100 ns t sudat data in setup time 100 50 10 ns t hddat data in hold time 0 0 0 ns t v output valid time 900 350 80 ns t oh output hold time 0 0 0 ns t buf bus free time between stop and start condition 1300 500 160 ns t susta repeated start condition setup time (scl high to sda low) 100 50 50 ns t hdsta start condition hold time (sda low to scl low) 100 50 50 ns t susto stop condition setup time (scl high to sda high) 600 50 50 ns t ns noise suppression input filter time 100 50 10 ns t timeout smbus timeout time 25 75 25 75 25 75 ms c load capacitive load for scl and sda lines (1) 400 400 100 pf
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 30 figure 7-1. smbus/i 2 c timing diagram 7.6 power-up conditions figure 7-2. power-up timing scl sda start condition stop condition repeated start condition start condition t sckh t sckh t sudat t sckl t hddat t oh t r t f t susto t v t buf t hdsta t susta in in out out in in symbol parameter min max units t por power-on reset time 1 ms v por power-on reset voltage range 1.6 v v cc v cc (min) v por (max) v por (min) time do not attempt device access during this time device access permitted t por
31 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 7.7 pin capacitance note: 1. not 100% tested (value guaranteed by design and characterization). 7.8 input test waveforms and measurement levels 7.9 output test load symbol parameter min max units ci/o (1) input/output capacitance (sda and alert pins) v i/o = 0v 8 pf cin (1) input capacitance (a 2-0 and scl pins) v in = 0v 6 pf ac input levels ac measurement level t r , t f < 5ns (10% to 90%) 0.9v cc 0.1v cc v cc 2 device under te s t 100pf
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 32 8. ordering information 8.1 atmel ordering code detail at30ts74-ss8m10-b atmel designator product family device type shipping carrier option slave address/customer specific option 30ts = digital temp. sensor b = bulk (tubes) t = tape and reel 10 = 1001 000x slave address 11 = 1001 001x slave address 12 = 1001 010x slave address 13 = 1001 011x slave address 14 = 1001 100x slave address 15 = 1001 101x slave address 16 = 1001 110x slave address 17 = 1001 111x slave address device grade voltage option package option m = 1.7v to 5.5v 8 = green, nipdau lead finish industrial high temperature range (?40c to +125c) accuracy guaranteed ss = 8-lead, 0.15" wide soic xm = 8-lead, 3.00 x 3.00mm msop ma = 8-pad, 2.00 x 3.00 x 0.60mm u = 4-ball wlcsp f = green, matte tin lead finish or snagcu ball industrial high temperature range (?40c to +125c) accuracy guaranteed
33 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 8.2 green package options (pb/halide-free/rohs compliant) notes: 1. the shipping carrier option code is not marked on the devices. 2. please contact atmel for availability of slave address options 011,100,101, 110, and 111. ordering code (1) package lead finish i 2 c address operating voltage max. freq. (khz) operation range at30ts74-ss8m-b 8s1 nipdau 1.7v to 5.5v 3400 industrial high temperature (-55c to +125c) at30ts74-ss8m-t at30ts74-xm8m-b 8xm at30ts74-xm8m-t at30ts74-ma8m-t 8ma2 at30ts74-ufm10-t 4u-3 snagcu (lead-free/ halogen-free) 1001 000x 1.7v to 5.5v 3400 industrial high temperature (-55c to +125c) at30ts74-ufm11-t 1001 001x at30ts74-ufm12-t 1001 010x at30ts74-ufm13-t (2) 1001 011x at30ts74-ufm14-t (2) 1001 100x at30ts74-ufm15-t (2) 1001 101x at30ts74-ufm16-t (2) 1001 110x at30ts74-ufm17-t (2) 1001 111x package type 8s1 8-lead, 0.15? wide, plastic gull wing small outline (jedec soic) 8xm 8-lead, 3.00mm x 3.00mm, plastic miniature small outline (msop) 8ma2 8-pad, 2.00mm x 3.00mm x 0.60mm, thermally enhanced plastic ultra thin dual flat no lead (udfn) 4u-3 4-ball, 2 x 2 grid array, wafer level chip scale (wlcsp)
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 34 9. part marking detail drawing no. rev. title 30ts74sm c 5/28/14 at30ts74sm , at30ts74 package marking information package mark contact: dl-cso-assy_eng@atmel.com aaaaaaaa t9 & @ atml8yww 8-lead soic 8-lead udfn t9 8&@ yxx 2.0 x 3.0 mm body note 2: package drawings are not to scale note 1: designates pin 1 at30ts74: package marking information catalog number truncation at30ts74 truncation code ###: t9 date codes slave address y = year m = month ww = work week of assembly % = slave address 4: 2014 8: 2018 a: january 02: week 2 a: address 000 e: address 100 5: 2015 9: 2019 b: february 04: week 4 b: address 001 f: address 101 6: 2016 0: 2020 ... ... c: address 010 g: address 110 7: 2017 1: 2021 l: december 52: week 52 d: address 011 h: address 111 country of assembly lot number grade/lead finish material @ = country of assembly aaa...a = atmel wafer lot number 8: industrial (c) (-40c to 125c)/nipdau trace code atmel truncation xx = trace code (atmel lot numbers correspond to code) at: atmel example: aa, ab.... yz, zz atm: atmel atml: atmel yww@ 8& xx t9 8-lead msop 4-ball wlcsp t9 yxx %& voltage & = voltage m: 1.7v min
35 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 10. packaging information 10.1 8s1 ? 8-lead jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: packagedrawings@atmel.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 36 10.2 8xm ? 8-lead msop title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 8xm tzd a 8xm, 8-lead, 3.0x3.0mm body, plastic thin shrink small outline package (tssop/msop) 3/1/11 common dimensions (unit of measure = mm) symbol min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.22 - 0.38 d 2.90 3.00 3.10 1 e 4.90 bsc e 1 2.90 3.00 3.10 1 e 0.65 bsc l 0.40 0.55 0.80 2 a e o c c a 1 n pin 1 e 1 1 a 2 3 side view end view detail 'a' top view seating plane 1 2 3 see detail "a" 2 l 4 1. one another within 0.10mm at seating plane. 4. 3. 2. formed leads shall be planar with respect to terminal positions are shown for reference only. for soldering to a substrate. dimension is the length of terminal protrusions shall not exceed 0.15mm per side. at datum plane -h- , mold flash or flash or protrusions, and are measured dimensions "d" & "e1" do not include mold notes: c 0.10 c l bsc 0.25 d c 0.20 b a 2x (n/2 tips) e 1 0.07 r. min 2 places -c- seating plane -h- -a- -b- s 0.05 5. datums -a- and -b- to be determined by datum plane -h- . bottom view n 3 2 1 8 0 c c o 4 b
37 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 10.3 8ma2 ? 8-pad udfn drawing no. rev. title gpc 8ma2 f 6/6/14 8ma2, 8-pad 2 x 3 x 0.6mm body, thermally enhanced plastic ultra thin dual flat no-lead package (udfn) ynz common dimensions (unit of measure = mm) symbol min nom max note a 0.50 0.55 0.60 a1 0.0 0.02 0.05 a2 - - 0.55 d 1.90 2.00 2.10 d2 1.20 - 1.60 e 2.90 3.00 3.10 e2 1.20 - 1.60 b 0.18 0.25 0.30 3 c 1.52 ref l 0.30 0.35 0.40 e 0.50 bsc k 0.20 - - top view side view bottom view package drawing contact: packagedrawings@atmel.com c e pin 1 id d 8 7 6 5 1 2 3 4 a a1 a2 d2 e2 e (6x) l (8x) b (8x) pin#1 id k 1 2 3 4 8 7 6 5 notes: 1. this drawing is for general information only. refer to drawing mo-229, for proper dimensions, tolerances, datums, etc. 2. the pin #1 id is a laser-marked feature on top view. 3. dimensions b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 4. the pin #1 id on the bottom view is an orientation feature on the thermal pad.
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 38 10.4 4u-3 ? 4-ball wlcsp drawing no. rev. title gpc 4u-3 a 10/23/13 4u-3, 4-ball 2x2 array wafer level chip scale package (wlcsp) gez common dimensions (unit of measure = mm) symbol min typ max note a 0.460 0.499 0.538 a1 0.164 - 0.224 a2 0.280 0.305 0.330 e see atmel for details d see atmel for details e1 0.400 bsc d1 0.400 bsc b 0.239 0.269 0.299 package drawing contact: packagedrawings@atmel.com top view side view ball side pin assignment matrix pin 1 a b 1 2 b a 2 1 a b 1 2 gnd vdd scl sda a b c j n 0.015 m c n 0.05 m cab d 0.015 c d 0.075 c d e e1 d1 a2 a1 a b * drawing not to scale
39 at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 11. errata 11.1 no errata
at30ts74 [preliminary datasheet] atmel-8897d-dts-at30ts74-datasheet_102014 40 12. revision history doc. rev. date comments 8897d 10/2014 update the dc characteristics and the ac characteristics tables. 8897c 09/2014 update power-up table and figure, and 8ma2 package drawing. 8897b 06/2014 update part markings and disclaimer page. 8897a 02/2014 initial document release.
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